1. Field of Invention
The present invention relates to an ultra-high efficiency printed circuit board (PCB) thermal conductive structure. More particularly, the present invention relates to a packaging method that utilizes an ultra-high efficiency thermal conductive structure.
2. Description of Related Art
In a module that contains an integrated circuit (IC), a large number of conductive wires normally emanate from the IC chip. Hundreds of connections have to be made externally to complete the circuit. In the past, there have been a variety of different circuit connections and packaging methods. The most commonly used packaging methods include planar packaging, hermetic and plastic chip carrier packaging, and grid array packaging.
Among the conventionally used packaging methods for IC chips, packages that includes a lead frame and a number of connective wires to connect between a semiconductor chip and external terminals are quite common. However, as the integrated circuit becomes more precise and interconnection becomes more complicated, the number of wires necessary for connecting the chip to the outside world soars. Therefore, conventional techniques that rely on wiring connection to a lead frame gradually become highly deficient. Consequently, new packaging method that can accommodate more wiring connections and more complicated circuits are being developed.
Currently, one type of packaging that can accommodate more wiring connections and more complicated circuits is a ball grid array (BGA). The BGA is a square array type of packaging where the wiring terminals are solder balls. These wiring terminals are fabricated into solder balls so they can be easily attached to the bonding pads of a printed wire board (or printed circuit board) or the surface of an appropriate device.
In reality, a conventional BGA type of connection can be regarded as a miniaturized multi-layered printed circuit board that connects an IC chip with external terminals through a series of internal conductors. These internal conductors are in turn connected by through holes in a metallic layer or metallic plugs.
In a conventional cavity-down type of BGA package, two or more metallic layers are compressed together and attached to a peripheral region of the substrate. These metallic layers are labeled as 108 and 112 in FIG. 1, which is a cross-sectional view showing a conventional ball grid array package. FIG. 1a is a magnified view showing the conductive layer of the first conventional package structure as shown in FIG. 1. The overall thickness of these metallic layers limits the maximum height of the solder balls. Since most IC chips have a thickness comparable or slightly thicker than the solder balls, the BGA package may act as a barrier to contacts between the solder balls and the printed circuit board. Hence, with the limitation on maximum height, it becomes preferable to mount the IC chip on one side of the substrate and then mount the solder balls on the opposite side of the substrate. However, with this arrangement, electrical connection between the chip and the solder balls must be achieved through metallic layers on both sides of the substrate and additional holes and plugs that penetrate through the substrate. Although this method can accommodate a large number of wiring connections, the manufacturing process is complicated and its production cost is high. For example, the substrate has to be specially made, holes and plugs have to be specially formed in the substrate, and the substrate and the metallic layers have to be specially joined together. At present, methods of cooling a package include the installation of a heat sink on the top of the chip, or drilling a hole underneath the chip that penetrates the substrate and the metallic layer. However, these methods not only increase the number of manufacturing steps, but also increase the cost of production as well.
To resolve the aforementioned problems, a package structure that involves multi-layered printed wire board and the use of adhesive glue (Prepreg) has been proposed by LSI Logic Corporation in U.S. Pat. No. 5,357,672. FIG. 1 is a cross-sectional view showing the proposed package structure. As shown in FIG. 1, silicon chip 101 is installed inside the central cavity. The central cavity is surrounded by printed circuit boards cut out and stacked on top of each other to form a tier structure. Near the edges of the tiers are bonding pads 105. Bonding wires are used to connect the bonding pad of the IC chip to the bonding pads 105 on the edge of the printed circuit board tier. Then, from the bonding pads 105, connections are made to respective bumps 109 through the printed circuit board and through holes 107. Finally, any signals coming from the IC chip can be sent to a main board. In the patent, the structure formed by gluing the printed circuit boards together is used as a substrate, and the silicon chip is mounted in the cavity enclosed by the substrate. Hence, the silicon chip and the bumps are on the same side of the substrate. Consequently, it is not necessary to employ two conductive layers on each side of the substrate to make connection.
FIG. 2 is a perspective view showing a second package structure by Washington Electric Corporation in U.S. Pat. No. 5,027,191. The IC chip 201 is installed inside the chip carrier. The IC chip 201 is connected to the bonding pads on the bonding ledge 205 through a series of bonding wires 203. Electrical connections are also made between the bonding pads on the bonding ledge 205 to the regularly spaced contact pads 207 on the surface of the chip carrier. Hence, electrical signals coming from the IC chip can be transmitted to the main board outside. The IC chip is facedown in this type of package design. Therefore, a heat sink can be installed on the bottom surface of the printed circuit board or on the top surface of the chip carrier in order to dissipate heat.
FIG. 3 is a cross-sectional view showing a type of IC package proposed by Motorola in one of its U.S. Patent applications. As shown in FIG. 3, the package has a plastic BGA (PBGA) structure having a silicon chip 301 directly attached to a central location of the printed circuit board substrate 300. A number of bonding wires 303 are used for connecting the bonding pads on the silicon chip 301 to the bonding pads 305 on the printed circuit board. The bonding pads 305 are in turn connected to the external solder balls 307 through printed circuits and via connections. The chip and the internal wires are enclosed within a protective plastic mold. In addition, a vent hole is formed underneath the silicon chip to increase heat dissipation.
Common features of the packages described above includes their capacity for accommodating vast quantities of conductive wires inside the package, or having their silicon chip and solder balls assembled on the same side of a substrate. However, all of them require the attachment of an external heat sink. Therefore, the package becomes bulkier and mass production of the package is more difficult. Moreover, to achieve full wiring connections, the printed circuit boards has to be shaped into a multi-tier structure. Hence, cost and difficulties of production are increased.
In light of the foregoing, there is a need to provide a method of improving the thermal conductive structure inside a printed circuit board.